MicroElectroMechanical Systems, referred to as MEMS, are an enabling technology. Generally speaking, MEMS devices are integrated circuits containing tiny mechanical, optical, magnetic, electrical, chemical, biological, or other, transducers or actuators. They are manufactured using high-volume silicon wafer fabrication techniques developed over the last 50 years for the microelectronics industry. Their resulting small size and low cost make them attractive for use in an increasing number of applications in consumer, automotive, medical, aerospace/defense, green energy, industrial, and other markets.
In general, a MEMS device must interact with a particular aspect of its environment while being protected from damage from the surroundings. For example, a micro mirror has to interact with light and with an electrical addressing signal while being protected from moisture and mechanical damage. An accelerometer has to be free to move in response to accelerated motion, but be protected from dirt and moisture, and perhaps also be kept under vacuum or low pressure to minimize air damping. In almost every application an electrical connection must be made between the MEMS transducer or actuator and an external Integrated Circuit, also referred to as IC, IC chip or microchip, in order to read the transducer signal or to address the actuator.
In an effort to drive down final device costs, there has been a push to eliminate much of the packaging and wire bonding by moving to wafer-scale packaging processes in which the MEMS and IC wafers are combined at the wafer level. There are basically two approaches to wafer-level integration of MEMS and IC. In one approach, the wafer containing the MEMS sensor element is bonded directly to a substrate wafer and covered with a non-functional lid wafer, such as described in U.S. Pat. No. 8,069,726 or U.S. Pat. No. 8,486,744. This approach requires modifying the IC wafer to accommodate the MEMS layout, leading to inefficiencies in the IC layout. Additionally, in order to electrically access the IC input/output signals (IC I/O), which are trapped between the MEMS device and the IC, it is necessary to mechanically trim the MEMS chips and caps after wafer-scale bonding to expose the bond pads. Wire bonding and packaging are still required, and therefore this approach is not truly wafer-level packaging.
Through-Silicon Vias (TSVs) have been proposed as a means of electrically connecting the MEMS and IC, either in the MEMS cap, as in U.S. Pat. No. 8,084,332 or in the IC, as in U.S. Pat. No. 8,486,744. The use of TSVs requires that the silicon being penetrated be limited in thickness to 100-200 microns. Using TSVs restricts devices to small vertical dimensions, placing limits on design and performance.
In the second approach to MEMS/IC wafer-level integration, the MEMS wafer fabrication is completed and the MEMS wafer is hermetically sealed separately from the IC wafer. This permits more flexibility in the design, fabrication, and bonding of both the MEMS and IC. Conducting TSVs or regions of silicon defined by insulating TSVs are used to provide electrical paths through one of the caps, and the MEMS and IC can be solder bonded together at the wafer level without using bond wires.
However, this still leaves the IC electrical connections trapped between the MEMS and the IC.
In order to bring the signals from the MEMS/IC interface to the outside, it has been proposed that TSVs be put in the IC wafer, prior to wafer-level bonding to the MEMS wafer. The backside of the IC wafer is then thinned and metalized. In this way the electrical signals can be routed between the MEMS and IC where necessary and out the back for IC I/O. This approach enables true wafer-scale MEMS/IC integration and packaging since the bonded wafers can be diced directly into chips that can be solder-bonded to a PC board without any additional wire bonding or packaging.
However, in order to put TSVs in an IC wafer, the IC design and process flow must be drastically modified to accommodate them. The TSV process involves etching holes or trenches into the IC wafer, coating the trench surface with an insulator, and filling the trench with a conductor such as polysilicon or metal. The TSVs are large (5-30 microns wide and up to 100-200 microns deep) compared to typically sub-micron IC feature sizes. Consequently large areas of the IC area must be reserved for the TSVs, resulting in less area-efficient and cost-efficient IC designs. Additionally, the TSV and IC processes are incompatible. IC transistors are fabricated in the top few microns of the wafer, while the TSV must penetrate through or nearly through the IC wafer. The additional TSV processes require additional non-IC fabrication tools such Deep Silicon Reactive Ion Etchers (DRIE) and electroplating. If the TSV fill is polysilicon, the TSVs must be placed in the IC wafer at the beginning of the IC process to avoid thermally affecting the IC implants during polysilicon deposition. If the TSVs are added at the end of the IC process, they must be filled with metal, such as electroplated Cu. Finally, an additional grind and polish step must be added to thin the IC wafer in order to make electrical contact to the TSVs. All these considerations add cost, either through additional process steps, inefficient use of IC silicon active area, or a limited choice of IC fabrication plants capable of performing the TSV steps. What is needed then is a low cost wafer-scale MEMS/IC integration and packaging method that provides a hermetic MEMS/IC component requiring no additional bond wires or external packaging for attachment to a board, and that is applicable to a wide variety of MEMS devices.